(1) Field of the Invention
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically, in the formation of self-aligned dual damascene interconnects and vias, which incorporates low dielectric constant intermetal dielectrics (IMD) and utilizes silylated top surface imaging (TSI) photoresist, with a single or multi-step selective reactive ion etch (RIE) process, to form trench/via opening.
(2) Description of the Related Art
As a background to the current invention, the damascene processing is an alternative method for fabricating planar interconnects. Damascene wiring interconnects (and/or studs) are formed by depositing a dielectric layer on a planar surface, patterning it using photolithography and oxide reactive ion etch (RIE), then filling the recesses with conductive metal. The excess metal is removed by chemical mechanical polishing (CMP), while the troughs or channels remain filled with metal. For example, damascene wiring lines can be used to form bit lines in DRAM devices, with processing similar to the formation of W studs in the logic and DRAM devices.
Key to the damascene processing approach is that the deposited conductive metal is deposited into a previously deposited patterned insulator. This is desirable because mask alignment, dimensional control, rework, and the etching process are all easier when applied to a dielectric rather than metal films. Damascene processing achieves these benefits by shifting the enhanced filling and planarization requirements from dielectric to metal films, and by shifting control over interconnect thickness from metal deposition to insulator patterning and metal CMP.
It remains a challenge in dual damascene processing to avoid damage to low dielectric constant insulators, i.e., organically based or carbon doped silicon dioxide materials. One significant problem is the degradation of the low dielectric constant materials during photoresist stripping with oxygen plasma ashing, wherein oxygen free radials react with carbon and hydrogen contained in low dielectric materials. Especially when patterning a via opening in the first level of a dual damascene, utilizing conventional photoresist processes, other deleterious effects can also occur to the low dielectric constant materials, e.g., bowing, profile distortion, increase in dielectric constant, and via poisoning are just some degradation effects. In addition, etching of via etch stop layers, i.e., silicon nitride, can cause gouging of the low dielectric constant organic material just below the stop layer. Post-etch solvent cleaning after the low dielectric material etch, can also attack the nitride stop layer/low dielectric constant material interface.
The related Prior Art background patents will now be described in this section.
U.S. Pat. No. 5,935,762 entitled xe2x80x9cTwo-Layered TSI Process for Dual Damascene Patterningxe2x80x9d granted Aug. 10, 1999 to Dai et al. describes a method for forming dual damascene patterns using a silylation process. A substrate is provided with a tri-layer of insulation formed thereon. A first layer of silylation photoresist is formed on the substrate and is imaged with a hole pattern by exposure through a mask. The hole pattern is then etched in the first photoresist. A second layer of photoresist is formed, and is imaged with a line pattern aligned with the previous hole pattern by exposure through a mask. The line pattern in the second photoresist is etched. The hole pattern in the first photoresist is transferred into the top layer of composite insulation first and then into the middle etch-stop layer by successive etching. Through a series of process steps, hole and line patterns are formed in the insulation layer, and metal is deposited in a dual damascene process.
U.S. Pat. No. 5,877,075 entitled xe2x80x9cDual Damascene Process Using Single Photoresist Processxe2x80x9d granted Mar. 2, 1999 to Dai et al. describes a dual damascene process using a silylation process with a single photoresist process. A substrate is provided with a tri-layer of insulation formed thereon. A layer of photoresist is formed on the substrate and is imaged with a hole pattern by exposure through a dark field mask. Hole is formed in the photoresist by a wet etch. As a key step, the photoresist is next subjected to post-exposure bake such that the sensitivity of the photoresist is still retained. The same photoresist layer is then exposed for the second time for aligned line patterning using a xe2x80x9cclear-fieldxe2x80x9d mask. The line patterned region is cross-linked by performing pre-silylation bake, which region in turn is not affected by the subsequent silylation process that forms a silicon rich mask in the field surrounding the hole and line patterns. Through a series of process steps, hole and line patterns are formed in the insulation layer, and metal is deposited in a dual damascene process.
U.S. Pat. No. 5,741,626 entitled xe2x80x9cMethod for Forming a Dielectric Tantalum Nitride Layer as an Antireflective Coating (ARC)xe2x80x9d granted Apr. 21, 1998 to Jain et al. describes a process with an anti-reflective Ta3N5 coating which can be used in a dual damascene structure and for I line or G line lithographies. In addition, the Ta3N5 coating may also be used as an etch stop and a barrier layer. A dual damascene structure is formed by depositing a first dielectric layer. A dielectric tantalum nitride layer is deposited on top of the first dielectric layer. A second dielectric layer is deposited on the tantalum nitride layer. A dual damascene opening is etched into the dielectric layers by patterning a first opening portion and a second opening portion using photolithography operations.
U.S. Pat. No. 5,906,911 entitled xe2x80x9cProcess of Forming a Dual Damascene Structure in a Single Photoresist Filmxe2x80x9d granted May 25, 1999 to Cote describes a dual damascene process using just one single layer of photoresist with two photomasks and selective silylation. The process includes the steps of forming a photoresist film on a substrate, pattern exposing the photoresist film to form a first pattern in the photoresist film, and forming an etch resistant layer in the first pattern. The photoresist film is pattern exposed a second time to form a second pattern in the photoresist film. After several more process steps and etching, dual damascene trench and via opens are formed.
It is a general object of the present invention to provide an improved method of forming semiconductor integrated circuit devices, and more specifically, in the formation of self-aligned dual damascene interconnects and vias, which incorporates low dielectric constant intermetal dielectrics (IMD) and utilizes silylated top surface imaging (TSI) photoresist, with a single or multi-step selective reactive ion etch (RIE) process, to form trench/via opening. The unexposed resist regions are removed by selective etching of this non-silylated material using either an oxygen plasma, or SO2 or SO3, plasmas or gases.
The low dielectric constant materials, utilized in this invention, consist of either an organic based material or a carbon doped silicon dioxide, and various combinations of the organic based material and carbon doped silicon dioxide. The organic based materials consists of, but are not restricted to, polyimide, xe2x80x9cFLARExe2x80x9d (source Allied Signal, now Honeywell), xe2x80x9cSILKxe2x80x9d (source Dow Chemical).
In the first embodiment of this invention, provided are the following: a semiconductor silicon substrate with an interlayer dielectric (ILD) layer thereon, with a level of metal wiring being defined and embedded in a layer of insulator. The first embodiment of the present invention starts with these conventional layers being provided. A bottom passivation layer is deposited on the metal wiring layer. Next, a low dielectric constant material layer is deposited on the bottom passivational layer. The low dielectric constant material consists of either an organic based material or a carbon doped silicon dioxide. In the first embodiment of this invention, a thin dielectric layer is deposited over the first layer of low dielectric constant material. The thin dielectric layer is selected from the group consisting of silicon dioxide, silicon nitride, silicon carbide, and silicon oxynitride. Next, top surface imaging (TSI) resist is placed over the thin dielectric layer. The resist is exposed to ultraviolet radiation, wavelength less than 248 nm, and using a photo mask, exposed regions and unexposed regions are formed. The exposed resist regions, later on in the process, become an etch stop for subsequent via formation, while the unexposed resist regions define the subsequent via opening.
The next set of process steps are key to the first embodiment of the present invention. The top surface imaging (TSI) resist, exposed regions are silylated becoming silicon rich containing material. The silylation is performed using HMDS (hexamethyldisilazane), in vapor phase, although solutions of 10% HMCTS (hexamethylcyclotrisilazane in xylene) can also cause the resist to be silylated. Next, a second layer of low dielectric constant material is deposited on the top surface imaging (TSI) resist, exposed silylated resist region and unexposed non-silylated resist region. As before, the low dielectric constant material consists of either an organic based material or a carbon doped silicon dioxide. Next, a cap layer of silicon nitride is deposited on the second layer of low dielectric constant material. Photoresist is applied and patterned over the cap layer, for subsequent trench opening in a dual damascene process. Note, that at this stage in the first embodiment of the present invention, both via region and trench region are now pattern defined for subsequent etching and trench/via opening in dual damascene processing.
The final set of process steps in the first embodiment of this invention are now described. A single or multi-step selective etching, reactive ion etch (RIE), is now performed, which is patterned by photoresist for a trench opening and silylated resist for an aligned via opening. The combined etching of the trench and via selectively etches through the top cap layer and through the second low dielectric layer. In addition, the unexposed resist, organic in nature, is selectively etched away. The silylated resist regions are resistant to the etch and act as a mask, patterning the opening for the via. Both exposed portions of the thin dielectric layer and exposed portions of the first layer of low dielectric material, are selectively etched away, stopping on the bottom passivation layer. Hence, after the selective etch and post etch cleaning, both trench opening and via opening are simultaneously formed for dual damascene processing. Subsequent dual damascene processing steps include: removal of the bottom passivation material in the contact via region and deposition of copper with removal of the excess copper by chemical mechanical polish (CMP), thus forming inlaid copper interconnects and contact vias.
In the second embodiment of this invention, provided are the following: a semiconductor silicon substrate with an interlayer dielectric (ILD) layer thereon, with a level of metal wiring being defined and embedded in a layer of insulator. The second embodiment of the present invention starts with these conventional layers being provided. A bottom passivation layer is deposited on the copper wiring layer. Next, a low dielectric constant material layer is deposited on the bottom passivation layer. The low dielectric constant material consists of either an organic based material or a carbon doped silicon dioxide. In the second embodiment of this invention, a thin dielectric layer is deposited over the first layer of low dielectric constant material. The thin dielectric layer is selected from the group consisting of silicon dioxide, silicon nitride, silicon carbide, and silicon oxynitride. Next, top surface imaging (TSI) resist is placed over the thin dielectric layer. The resist is exposed to ultraviolet radiation, wavelength less than 248 nm, and using a photo mask, exposed regions and unexposed regions are formed. The exposed resist regions, later on in the process, become an etch stop for subsequent via formation. The top surface imaging (TSI) resist is silylated becoming silicon rich containing material. The silylation is performed using HMDS (hexamethyldisilazane), in vapor phase, although solutions of 10% HMCTS (hexamethylcyclotrisilazane in xylene) can also cause the resist to be silylated. The unexposed resist regions are removed by selective etching of this non-silylated material using either an oxygen plasma, or SO2 or SO3, plasmas or gases. Note, that this process then defines the subsequent via opening. The sensitive organic low dielectric constant material is protected from this etch process by the thin dielectric.
The next set of processing steps in the second embodiment of the present invention are now summarized. A second layer of low dielectric constant material is deposited on the top surface imaging (TSI) resist, that is, the exposed silylated resist region and over the thin dielectric layer. As before, the low dielectric constant material consists of either an organic based material or a carbon doped silicon dioxide. Next, a cap layer of silicon nitride is deposited on the second layer of low dielectric constant material. Photoresist is applied and patterned over the cap layer for subsequent trench opening, in a dual damascene process. Note, that at this stage in the second embodiment of the present invention, both via region and trench region are now pattern defined for subsequent etching and trench/via opening in dual damascene processing.
The final set of process steps in the second embodiment of this invention are now described. A single or multi-step selective etching, reactive ion etch (RIE), is performed which is patterned by photoresist for trench opening and silylated resist for an aligned via opening. The single or multi-step selectively etches through the top cap layer and through the second low dielectric layer. The silylated resist regions are resistant to the etch and act as a mask, patterning the opening for the via. Both exposed portions of the thin dielectric layer and exposed portions of the first layer of low dielectric material, are selectively etched away, stopping on the bottom passivation layer. Hence, after the selective etch and post etch cleaning, trench opening and via opening are simultaneously formed for dual damascene processing. Subsequent dual damascene processing steps include: removal of the bottom passivation material in the contact via region and deposition of copper with removal of the excess copper by chemical mechanical polish (CMP), thus forming inlaid copper interconnects and contact vias.
In the third embodiment of this invention, provided are the following: a semiconductor silicon substrate with an interlayer dielectric (ILD) layer thereon, with a level of metal wiring being defined and embedded in a layer of insulator. The third embodiment of the present invention starts with these conventional layers being provided. A bottom passivation layer is deposited on the metal wiring layer. Next, a low dielectric constant material layer is deposited on the bottom passivation layer. The low dielectric constant material consists of either an organic based material or a carbon doped silicon dioxide. In the third embodiment of this invention, a layer of thin dielectric utilized earlier is omitted, provided adhesion between the first layer of low dielectric constant material, mentioned above, and subsequent resist material, is adequate. Next, top surface imaging (TSI) resist is placed on the low dielectric constant material layer. The resist is exposed to ultraviolet radiation, wavelength less than 248 nm, and using a photo mask, exposed regions and unexposed regions are formed. The exposed resist regions, later on in the process, become an etch stop for subsequent via formation, while the unexposed resist regions define the subsequent via opening.
The next set of process steps are key to the third embodiment of the present invention. The top surface imaging (TSI) resist, exposed regions are silylated becoming silicon rich containing material. The silylation is performed using HMDS, (hexamethyldisilazane), in vapor phase, although solutions of 10% HMCTS (hexamethylcyclotrisilazane in xylene) can also cause the resist to be silylated. Next, a second layer of low dielectric constant material is deposited on the top surface imaging (TSI) resist, exposed silylated resist region and unexposed non-silylated resist region. As before, the low dielectric constant material consists of either an organic based material or a carbon doped silicon dioxide. Next, a cap layer of silicon nitride is deposited on the second layer of low dielectric constant material. Photoresist is applied and patterned over the cap layer, for subsequent trench opening in a dual damascene process. Note, that at this stage in the third embodiment of the present invention, both via region and trench region are now pattern defined for subsequent etching and trench/via opening in dual damascene processing.
The final set of process steps in the third embodiment of this invention are now described. A single or multi-step selective etching, reactive ion etch (RIE), is performed, which is patterned by photoresist for trench opening and silylated resist for an aligned via opening. The single or multi-step selectively etches through the top cap layer and through the second low dielectric layer. In addition, the unexposed resist, organic in nature, is selectively etched away. The silylated resist regions are resistant to the etch and act as a mask, patterning the opening for the via. Exposed portions of the first layer of low dielectric material, are selectively etched away, stopping on the bottom passivation layer. Hence, after the selective etch and post etch cleaning, trench opening and via opening are simultaneously formed for dual damascene processing. Subsequent dual damascene processing steps include: removal of the bottom passivation material in the contact via region and deposition of copper with removal of the excess copper by chemical mechanical polish (CMP), thus forming inlaid copper interconnects and contact vias.
In the fourth embodiment of this invention, provided are the following: a semiconductor silicon substrate with an interlayer dielectric (ILD) layer thereon, with a level of metal wiring being defined and embedded in a layer of insulator. The fourth embodiment of the present invention starts with these conventional layers being provided. A bottom passivation layer is deposited on the copper wiring layer. Next, a low dielectric constant material layer is deposited on the bottom passivation layer. The low dielectric constant material consists of either an organic based material or a carbon doped silicon dioxide. In the fourth embodiment of this invention, a layer of thin dielectric utilized earlier is omitted, provided adhesion between the first layer of low dielectric constant material, mentioned above, and subsequent resist material, is adequate. Next, top surface imaging (TSI) resist is placed on the low dielectric constant material layer. The resist is exposed to ultraviolet radiation, wavelength less than 248 nm, and using a photo mask, exposed regions and unexposed regions are formed. The exposed resist regions, later on in the process, become an etch stop for subsequent via formation, while the unexposed resist regions define the subsequent via opening. The top surface imaging (TSI) resist is silylated becoming silicon rich containing material. The silylation is performed using HMDS (hexamethyldisilazane), in vapor phase, although solutions of 10% HMCTS (hexamethylcyclotrisilazane in xylene) can also cause the resist to be silylated. The unexposed resist regions are removed by selective etching of this non-silylated material using SO2 or SO3, plasmas or gases. Note, that this process then defines the subsequent via opening. The sensitive organic low dielectric constant material is now exposed to etching in this process, hence the designated use of SO2 or SO3, in plasmas, or gases, is specified.
The next set of processing steps in the fourth embodiment of the present invention are now summarized. A second layer of low dielectric constant material is deposited on the top surface imaging (TSI) resist, that is, exposed silylated resist region and on the exposed portion of the first low dielectric material. As before, the low dielectric constant material consists of either an organic based material or a carbon doped silicon dioxide. Next, a cap layer of silicon nitride is deposited on the second layer of low dielectric constant material. Photoresist is applied and patterned over the cap layer for subsequent trench opening, in a dual damascene process. Note, that at this stage in the fourth embodiment of the present invention, both via region and trench region are now pattern defined for subsequent etching and trench/via opening in dual damascene processing.
The final set of process steps in the fourth embodiment of this invention are now summarized. A single or multi-step selective etching, reactive ion etch (RIE), is performed which is patterned by photoresist for trench opening and silylated resist for via opening. The single or multi-step selectively etches through the top cap layer and through the second low dielectric layer. The silylated resist regions are resistant to the etch and act as a mask, patterning the opening for the via. Exposed portions of the first layer of low dielectric material, are selectively etched away, stopping on the bottom passivation layer. Hence, after the selective etch and post etch cleaning, trench opening and via opening are simultaneously formed for dual damascene processing. Subsequent dual damascene processing steps include: removal of the bottom passivation material in the contact via region and deposition of copper with removal of the excess copper by chemical mechanical polish (CMP), thus forming inlaid copper interconnects and contact vias.
This invention has been summarized above and described with reference to the preferred embodiments. Some processing details have been omitted and are understood by those skilled in the art. More details of this invention are stated in the xe2x80x9cDESCRIPTION OF THE PREFERRED EMBODIMENTSxe2x80x9d section.